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| White Electronic Designs WED2DG472512V-D2 ADVANCED* 16MB (4x512Kx72) SYNC BURST-PIPELINE, DUAL KEY DIMM FEATURES 4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V 10% Operation Frequency(s): 200, 166, 150, and 133MHz Access Speed(s): tKHQV = 3.0, 3.5, 3.7, and 4.0ns Common Data I/O High Capacitance (30pF) Drive, at Rated Access Speed Single Total Array Clock Multiple Vcc and Gnd for Improved Noise Immunity * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. DESCRIPTION The WED2DG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72. The Module contains sixteeen (16) Synchronous Burst RAM devices, packaged in the industry stan dard JEDEC 14mmx20mm TQFP placed on a Multilayer FR4 Substrate. The Module Architecture is defined as a Sync/SyncBurst, Pipeline, with support for either linear or sequential burst. This Module provides high performance, 3-1-1-1 accesses when used in Burst Mode, and when used in Synchronous Only Mode, provides a high performance, data access every second cycle. Synchronous Only operations are performed via strapping ADSC# Low, and ADSP#/ADV# High, which provides for Ultra Fast Accesses in Read Mode while providing for internally self-timed Early Writes. Synchronous/Synchronous Burst operations are in relation to an externally supplied clock, Registered Address, Registered Global Write, Registered Enables as well as an Asynchronous Output Enable. This Module has been defined with full flexibility, which allows individual control of each of the eight bytes, as well as Quad Words in both Read and Write Operations. White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED FIG. 1 PIN DESCRIPTION PIN CONFIGURATION PIN IDENTIFIER DQ0 - DQ63 DQP0 - DQP7 A0 - A18 Input/Output Bus Parity Bits Address Bus Module Enable Synchronous Bank Enables Byte Write Mode Enable Byte Write Enables Array Clock Synchronous Global Write Enable Asynchronous Output Enable Bank Sleep Mode Enables 3.3V Power Supply Gnd VSS A0 A16 A2 A14 VCC A4 A12 A6 A10 VSS A8 RFU E4# E2# VSS MODE EM# GW# RFU VCC BW4# BW3# BW8# BW7# ADSC# ADSP# VSS NC VCC DQ0 DQ1 DQ2 DQ3 VSS ZZ1 VCC DQ8 DQ9 DQ10 DQ11 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 VSS A17 A1 A15 A3 VCC A13 A5 A11 A7 VSS A9 A18 E1# E3# VSS CK VSS G# BWE# VCC BW2# BW1# BW6# BW5# VSS ADV# VSS DQP0 VCC DQ7 DQ6 DQ5 DQ4 VSS DQP1 VCC DQ15 DQ14 DQ13 DQ12 VSS EM# NC VCC DQ16 DQ17 DQ18 DQ19 VSS ZZ2 VCC DQ24 DQ25 DQ26 DQ27 VSS NC VCC DQ32 DQ33 DQ34 DQ35 VSS ZZ3 VCC DQ40 DQ41 DQ42 DQ43 VSS NC VCC DQ48 DQ49 DQ50 DQ51 VSS ZZ4 VCC DQ56 DQ57 DQ58 DQ59 VSS 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 DQP2 VCC DQ23 DQ22 DQ21 DQ20 VSS DQP3 VCC DQ31 DQ30 DQ29 DQ28 VSS DQP4 VCC DQ39 DQ38 DQ37 DQ36 VSS DQP5 VCC DQ47 DQ46 DQ45 DQ44 VSS DQP6 VCC DQ55 DQ54 DQ53 DQ52 VSS DQP7 VCC DQ63 DQ62 DQ61 DQ60 VSS E1#, E2#, E3#, E4# BWE# BW1# - BW8# CK GW# G# ZZ1, ZZ2, ZZ3, ZZ4 Vcc Vss White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED FIG. 2 FUNCTIONAL BLOCK DIAGRAM ADDR BW8# BW7# BW6# BW5# BW4# BW3# BW2# BW1# BWE# E4# E3# E2# E1# BW8# BW7# BW6# BW5# BW4# BW3# BW2# BW1# BWE# E4# E3# E2# E1# ADV# BW4# BW3# BW2# BW1# BWE# E1# ZZ1 GW# G# ADSP# ADSC# 512K x 18 SBPL SCD ADV# BW4# BW3# BW2# BW1# BWE# E2 ZZ2 GW# G# ADSP# ADSC# 512K x 18 SBPL SCD ADV# BW4# BW3# BW2# BW1# BWE# E3 ZZ3 GW# G# ADSP# ADSC# 512K x 18 SBPL SCD ADV# BW4# BW3# BW2# BW1# BWE# E4 ZZ4 GW# G# ADSP# ADSC# 512K x 18 SBPL SCD 512K x 18 SBPL SCD 512K x 18 SBPL SCD 512K x 18 SBPL SCD 512K x 18 SBPL SCD Data (DQ) GW# G# BW8# BW7# BW6# BW5# BWE# E1# ZZ1 BW8# BW7# BW6# BW5# BWE# E2# ZZ2 BW8# BW7# BW6# BW5# BWE# E3# ZZ3 BW8# BW7# BW6# BW5# BWE# E4# ZZ4 MODE ADSP# ADSC# ADV# ZZ1 ZZ2 ZZ3 ZZ4 CK 512K x 18 SBPL SCD 512K x 18 SBPL SCD 512K x 18 SBPL SCD 512K x 18 SBPL SCD GW# G# ADSP# ADSC# ADV# 512K x 18 SBPL SCD GW# G# ADSP# ADSC# ADV# 512K x 18 SBPL SCD GW# G# ADSP# ADSC# ADV# 512K x 18 SBPL SCD GW# G# ADSP# ADSC# ADV# 512K x 18 SBPL SCD U1 -U8 EQUAL LENGTH NET ROUTES White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs SYNC BURST - TRUTH TABLE Operation E1# Deselected Cycle, Power Down; Bank 1 H Deselected Cycle, Power Down; Bank 2 X Read Cycle, Begin Burst; Bank 1 L Read Cycle, Begin Burst; Bank 1 L Read Cycle, Begin Burst, Bank 2 H Read Cycle, Begin Burst; Bank 2 H Write Cycle, Begin Burst; Bank 1 L Write Cycle, Begin Burst; Bank 2 H Read Cycle, Begin Burst; Bank 1 L Read Cycle, Begin Burst; Bank 1 L Read Cycle, Begin Burst; Bank 2 H Read Cycle, Begin Burst; Bank 2 H Read Cycle, Continue Burst; Bank 1 X Read Cycle, Continue Burst; Bank 1 X Read Cycle, Continue Burst; Bank 2 H Read Cycle, Continue Burst; Bank 2 H Read Cycle, Continue Burst; Bank 1 H Read Cycle, Continue Burst; Bank 1 H Read Cycle, Continue Burst; Bank 2 H Read Cycle, Continue Burst; Bank 2 H Write Cycle, Continue Burst; Bank 1 X Write Cycle, Continue Burst; Bank 1 H Write Cycle, Continue Burst; Bank 2 H Write Cycle, Continue Burst; Bank 2 H Read Cycle, Suspend Burst; Bank 1 X Read Cycle, Suspend Burst; Bank 1 X Read Cycle, Suspend Burst; Bank 2 H Read Cycle, Suspend Burst; Bank 2 H Read Cycle, Suspend Burst; Bank 1 H Read Cycle, Suspend Burst; Bank 1 H Read Cycle, Suspend Burst; Bank 2 H Read Cycle, Suspend Burst; Bank 2 H Write Cycle, Suspend Burst; Bank 1 X Write Cycle, Suspend Burst; Bank 1 H Write Cycle, Suspend Burst; Bank 2 H Write Cycle, Suspend Burst; Bank 2 H E2# X H H H L L H L H H L L H H X X H H H H H H X H H H X X H H H H H H X H E3# E4# ADSP# ADSC# ADV# X L X X L X L X X L X X L X X L X X H L X H L X H L X H L X H L X H L X X H L X H L X H L X H L X H L X H L X H L X H L H H L X H L H H L X H L H H H H H H H H H H H H X H H X H H X H H X H H H H H X H H H H H X H H WED2DG472512V-D2 ADVANCED GW# X X X X X X L L H H H H H H H H H H H H L L L L H H H H H H H H L L L L G# X X L H L H X X L H L H L H L H L H L H X X X X L H L H L H L H X X X X CK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z Q High-Z D D D D Q High-Z Q High-Z Q High-Z Q High-Z D D D D Addr. Used None None External External External External External External External External External External Next Next Next Next Next Next Next Next Next Next Next Next Current Current Current Current Current Current Current Current Current Current Current Current Note A: All truth Table Functions Repeat for Bank 3 (E3#) and Bank 4 (E4#). SYNCHRONOUS ONLY - TRUTH TABLE Operation Synchronous Write - Bank 1 Synchronous Read - Bank 1 Synchronous Write - Bank 2 Synchronous Read - Bank 2 Synchronous Write - Bank 3 Synchronous Read - Bank 3 Synchronous Write - Bank 4 Synchronous Read - Bank 4 Snooze Mode E1# L L H H H H H H X E2# H H L L H H H H X E3# H H H H L L H H X E4# H H H H H H L L X GW# L H L H L H L H X G# H L H L H L H L X ZZ L L L L L L L L H X High-Z High-Z High-Z High-Z CK DQ High-Z White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 4 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com No te A White Electronic Designs ABSOLUTE MAXIMUM RATINGS* Voltage on Vcc Relative to Vss VIN Storage Temperature Operating Temperature (Commercial) Operating Temperature (Industrial) Short Circuit Output Current -0.3V to +4.6V -0.3V to Vcc +0.5V -55C to + 125C 0C to +70C -40C to +85C 100mA WED2DG472512V-D2 ADVANCED RECOMMENDED DC OPERATING CONDITIONS Parameter Supply Voltage Supply Voltage Input High Input Low Input Leakage Output Leakage Sym Vcc Vss VIH VIL ILI ILo Min 3.3 0 2.0 -0.3 -2 -2 Typ 3.3 0 3.0 0 1 1 Max 3.6 0 Vcc+0.3 0.3 2 2 Units V V V V mA mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS READ CYCLE Max Description Power Supply Current Power Supply Current Device Selected, No Operation Snooze Mode CMOS Standby Clock Running-Deselect Sym Icc1 Icc IccZZ Icc3 IccK Typ 1.9 875 270 500 900 5.0 2.7 1.8 350 700 1.1 6.0 2.5 1.8 350 700 1.1 6.5 2.4 1.3 350 700 1.0 7.0 2.3 1.3 350 700 1.0 Units A A mA mA A AC TEST LOAD DQ Output Z0 == 50 Z0 50W AC TEST CONDITIONS Input Pulse Levels Input and Output Timing Ref. RL = 50 Vss to 3.0V 1.25V See figure at left Output Test Equivalencies VL = 1.25V Output Test Equivalencies White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED SYNC-BURST READ CYCLE PARAMETERS 3.0ns Description Frequency Clock Cycle Time Clock High Time Clock Low Time Clock to Output Valid Clock to Output Invalid Clock to Output Low-Z Output Enable to Output Valid Output Enable to Output Low-Z Output Enable to Output High-Z Address Setup Bank Enable Setup Address Hold Bank Enable Hold Sym fMAX tKC tKH tKL tKQ tKQX tKQLZ tOEQ tOELZ tOEHZ tS tS tH tH 1.5 1.5 0.5 0.5 1.25 0 1.25 0 2.5 1.5 1.5 0.5 0.5 3 5.0 2 2 3 1.25 0 1.25 0 3.5 1.8 1.8 0.5 0.5 4 Min Max 200 6.0 2.4 2.4 3.5 1.25 0 1.25 0 3.5 2.0 2.0 0.5 0.5 4 3.7 1.25 0 1.25 0 4 5 Min 3.5ns Max 166 6.5 2.5 Min 3.7ns Max 150 7.0 3 3 4 Min 4.0ns Max 133 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns SYNC-BURST WRITE CYCLE PARAMETERS 3.0ns Description Frequency Clock Cycle Time Clock High Time Clock Low Time Address Setup Address Hold Bank Enable Setup Bank Enable Hold Global Write Enable Setup Global Write Enable Hold Data Setup Data Hold Sym fMAX tKC tKH tKL tS tH tS tH tS tH tS tH 5.0 2 2 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 Min Max 200 6.0 2.4 2.4 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 Min 3.5ns Max 166 6.5 2.7 2.7 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 Min 3.7ns Max 150 7.0 3 3 2.0 0.5 1.8 0.5 2.0 0.5 2.0 0.5 Min 4.0ns Max 133 Units MHz ns ns ns ns ns ns ns ns ns ns ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED FIG. 3 SYNC-BURST READ CYCLE tKC tKH tKL CK tS ADSP# tH ADSC# tS Ax A1 tH A2 BWx#, BWE#, GW# EM#, E# tS ADV# tH G# tKQ tKQLZ DQx tOEQ tOELZ Q(A1) tKQ Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) Single Read Burst Read White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED FIG. 4 SYNC-BURST WRITE CYCLE CK tS ADSP# tH ADSC# tS Ax A1 tH A2 A3 BWx#, BWE# GW# EM#, E# tS ADV# tH G# tOEHZ tKQX DQx Q D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2) Single Write Burst Write Burst Write White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED FIG. 5 SYNC-BURST READ/WRITE CYCLE CK tS ADSP# tH ADSC# tS Ax A1 A2 tH A3 A4 A5 BWx#, BWE#, GW# EM#, E# ADV# G# DQx Q(A1) Q(A2) D(A3) Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Single Read Single Write Burst Read Burst Write White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com White Electronic Designs WED2DG472512V-D2 ADVANCED PACKAGE DIMENSIONS: 168 DUAL KEY DIMM 5.255 MAX. 0.195 MAX. 0.157 (2x) 195 1.500 MAX. 0.700 P1 0.078 (2X) 0.450 0.575 0.350 0.925 0.250 1.450 1.700 2.150 0.125 0.050 TYP. 0.225 MIN. ALL DIMENSIONS ARE IN INCHES ORDERING INFORMATION Part Number WED2DG472512V5D2 WED2DG472512V6D2 WED2DG472512V65D2 WED2DG472512V7D2 Configuration 16 MB (4 x 512K x 72) 16 MB (4 x 512K x 72) 16 MB (4 x 512K x 72) 16 MB (4 x 512K x 72) Description Sync-Burst Pipeline Sync-Burst Pipeline Sync-Burst Pipeline Sync-Burst Pipeline Voltage (V) 3.3V 3.3V 3.3V 3.3V Frequency 200MHz 166MHz 150MHz 133MHz Package 168 Dual Key DIMM 168 Dual Key DIMM 168 Dual Key DIMM 168 Dual Key DIMM White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2000 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.whiteedc.com |
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